1. Field of the Invention
The present invention relates to a scanning line converter to make scanning lines inconspicuous even in a large sized picture by converting the number of scanning lines per frame of a television signal, used in NTSC or PAL color television systems, into a multiple number thereof.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional scanning line converter. With reference to FIG. 1, 1 is a decoder which extracts a video signal, horizontal synchronizing signal HD and vertical synchronizing signal VD from a television signal; 2 is an analog/digital converter (hereinafter referred to as A/D converter) which digitizes a video signal; 3 is a video memory which memorizes each field, frame or line of the digitized video signal; 4 is a digital/analog converter (hereinafter referred to as D/A converter) which converts a digital video signal into an analog video signal; 12 is a phase comparator which compares the phase of the horizontal synchronizing signal HD with that of the output of a frequency demultiplying counter 15; 13 is a low-pass filter; 14 is a voltage control oscillator (hereinafter referred to as VCO); 11 is a timing pulse generating circuit for producing a control signal or a synchronizing signal for the video memory 3.
Following are the explanations of operation. The decoder 1 converts a television signal into a video signal with chrominance information of R, G and B, as well as extracting a horizontal synchronizing signal HD and a vertical synchronizing signal VD. The phase comparator 12 compares the phase of the separated horizontal synchronizing signal HD with that of a pulse H produced by the frequency demultiplying counter 15. An error voltage obtained by the phase comparison is supplied to VCO 14 through a low-pass filter 13. An oscillation frequency of VCO 14 is varied according to the error voltage. A frequency of a clock pulses RCK produced by VCO 14 is demultiplied with the frequency demultiplying counter 15. The frequency demultiplying counter 15 demultiplies the frequency of the clock pulses RCK by a factor of two, to produce write-clock-pulses WCK for writing video memory, and further demultiplies the frequency of the pulses WCK to produce the pulses H of which the phases are compared with that of the horizontal synchronizing signal HD by the phase comparator 12, and moreover it produces pulses 2H which have the double frequency of H and supplies them to the timing pulse generating circuit 11. The phase comparator 12 the low-pass filter 13, VCO 14 and the frequency demultiplying counter 15 constitute a phase-locked-loop PLL, and it produces read-clock-pulses RCK, write-clock-pulses WCK and double-speed horizontal synchronizing pulses 2H in synchronism with horizontal synchronizing pulses HD.
The video signals decoded by the decoder 1 are converted to digital data through the A/D converter 2, and after that the data are written into the video memory 3 in synchronism with the write-clock-pulses WCK. The read-out of the video memory 3 is performed two times for each line in synchronism with the read-clock-pulses RCK whose frequency is double the frequency of the write-clock-pulses WCK. The data thus read-out are converted to analog data through the D/A converter 4 to obtain a video signal of double speed. The roughness of a picture on a CRT can be made less conspicuous by converting the number of scanning lines to a number double the original.
A conventional scanning line converter is constituted as described above and write-clock-pulses, read-clock-pulses and double-speed horizontal synchronizing signal are produced with the phase-locked-loop, but if the frequency of the synchronizing signal in a television signal is not stable, it becomes impossible to supply stable write-clock-pulses, read-clock-pulses or the double-speed horizontal synchronizing signal, which may cause trouble in scanning line conversion. This is one of the drawbacks of the conventional scanning line converter.